JD : Senior/ Lead Verification Engineer
Role Summary :
Build world class, cutting edge team, processes and verification architecture for high performance memory interface IP and associated testchips.
Detailed Requirements :
- Lead a team of verification engineers to delivering high quality DDR and other memory interface PHY’s.
- Ensure skilling of the team both in terms of tools and protocol exposure
- Ensure growth and career development of team
- Manage project execution and deadlines and deliver high verified IP in a timely manner
- Build an agile verification environment with high levels of reuse and modularity
- Develop coverage and other necessary metrics to objectively define the quality of the verification effort
- Be a expert on memory interface protocols and drive verification well and beyond “standard” practices
- Drive channel and jitter modelling
- Drive firmware development
- Maintain sophisticated regression suites with varying levels of exhaustiveness
- Carefully map out a randomization strategy
- Create verification collateral that will accompany the IP
- Interact with CTO and other technical leaders in the company to define verification roadmap
- Drive formal verification strategy and execution
- Support IP through design phase as well as post-silicon
- Understand and optimally use available VIP
- Plan team composition and growth
Eductational qualifications :
- Bachelors degree in electronics/computer engineering/computer science
- Masters degree in electronics/computer engineering/computer science preferred
Experience :
Technical qualifications :
- Experience in leading verification for high performance memory interface IP like LPDDRx,DDRx, HMBx and/or GDDRx etc.. from scratch to post-silicon support (end-to-end verification cycle) and good understanding of associated protocols is very preferable
- Prior experience in leading high-performance verification teams and delivering on aggressive deadlines. Must be a hands-on technical leader
- Strong skill and experience in system verilog and UVM
- Strong skill and experience in simulators (NCSim/VCS/ModelSim/Questa)
- Strong scripting skills in python, perl, C and C++
- Experience and exposure to standard industry protocols like AHB/AXI/ACE/ACE/APB/Jtag
- Experience with using complex VIP, scoreboards, trackers, assertions etc.
- Experience with gate level simulation, power aware simulation and formal verification